Aditya Sodhani

PhD student, Electrical and Computer Engineering, University of Minnesota
Advised by Prof. Keshab K. Parhi

I work on the classical side of fault-tolerant quantum computing: decoders that run in real time inside the cryostat, next to the qubits, and compilers that make the encoding circuits of quantum error-correcting codes cheaper to run.

Before my PhD, I spent two years at Qualcomm as a hardware engineer working on the performance of Snapdragon memory subsystems, and six months at Micron as a design verification engineer. I hold an M.E. in Microelectronics (gold medalist) and a B.E. in Electrical and Electronics Engineering from BITS Pilani.

I expect to graduate in May 2028 and am interested in research roles where quantum error correction meets computer architecture and VLSI.

Aditya Sodhani

News

Research

My research asks how much of quantum error correction can be done by small, fast classical hardware next to the qubits, and how to make the circuits that error correction needs cheaper. It runs in three threads.

Decoders inside the cryostat

In a superconducting quantum computer the qubits sit at about 20 mK while the decoder that interprets their error syndromes sits at room temperature, so every syndrome bit must cross the refrigerator's wiring. Beyond a few hundred logical qubits, the bandwidth of that link and the cooling budget of the 4 K stage become the bottleneck.

I design local decoders that live at 4 K, resolve the common error patterns in a fixed number of cycles, and forward only the hard cases to a room-temperature decoder. My two-stage lookup-table decoder for the surface code handles more than 97% of syndrome rounds locally at practical error rates, at an estimated 12.8 µW per decoder from a cryo-CMOS model of its 22 nm RTL, and a Monte Carlo comparison against minimum-weight perfect matching shows no loss in threshold from distance 3 to 17. The same approach extends to IBM's Bivariate Bicycle qLDPC codes with BP+OSD as the fallback.

300 K · ROOM TEMPERATURE 4 K STAGE 20 mK · QUBITS Global decoder matching / BP+OSD, software Local decoder fixed-latency RTL, µW budget Surface-code patch syndromes every ~1 µs all syndromes hard cases only
A two-level decoding hierarchy: the local decoder at 4 K keeps most syndromes off the link to room temperature.

Low-overhead encoder circuits for quantum LDPC codes

Preparing the logical state of a quantum LDPC code takes an encoder circuit whose CNOT count and depth decide how much noise enters before correction even begins. I treat encoder synthesis as a circuit-optimization problem: beam search over GF(2) row operations for entanglement-assisted QC-LDPC codes, a two-sided Hamming descent that resynthesizes the CNOT block of any CSS LDPC encoder, and a hardware-aware back end that routes, selects and schedules circuits using a noise model of the target device.

Across the benchmarks this cuts CNOT counts by 54% in aggregate and routed two-qubit depth by up to 71%. For nonbinary (qudit) stabilizer codes, I developed a framework over new generating gate sets that reduces encoder gate counts by up to 44%.

Six-stage encoder synthesis pipeline: two-sided Hamming descent, commutation re-layering, count-depth Pareto frontier, SABRE routing, noise-aware selection, live-range scheduling.
The six-stage pipeline: logical synthesis on the left, hardware-aware adaptation on the right.

Learned decoders on experimental data

Lookup tables and matching are hand-designed; a learned decoder can pick up the correlated noise of a real device. I trained a 21K-parameter recurrent transformer, quantized to INT4 so that it could one day run next to the qubits, on Google's experimental Sycamore surface-code data. On 35,000 held-out shots it reaches a 5.2% lower logical error rate than minimum-weight perfect matching.

Sycamore syndrome rounds Recurrent transformer 21K params · INT4 Logical correction
A compact learned decoder trained and tested on measured data from a real processor.

Publications

Noise-Aware Synthesis of Quantum LDPC Encoder Circuits via Two-Sided Hamming Descent

Aditya Sodhani, Keshab K. Parhi

arXiv:2607.04462, July 2026 Preprint · under review

arXiv PDF
BibTeX
@misc{sodhani2026hamming,
  author        = {Sodhani, Aditya and Parhi, Keshab K.},
  title         = {Noise-Aware Synthesis of Quantum {LDPC} Encoder Circuits via Two-Sided {Hamming} Descent},
  year          = {2026},
  eprint        = {2607.04462},
  archivePrefix = {arXiv}
}

Resynthesizes the CNOT block of CSS LDPC encoders with two-sided Hamming descent, then routes, selects and schedules the circuit with a hardware noise model. Across Bivariate Bicycle, hypergraph-product and entanglement-assisted codes: 53.8% fewer CNOTs in aggregate (up to 68% on Bivariate Bicycle codes), up to 71% lower routed two-qubit depth, and up to 13.7% lower preparation failure from live-range scheduling.

Optimizing Encoder Circuits of Entanglement-Assisted Quantum LDPC Codes via Beam Search

Aditya Sodhani, Pavan Kumar, Shayan Srinivasa Garani, Keshab K. Parhi

IEEE Transactions on Circuits and Systems II: Express Briefs, 2026

DOI arXiv PDF
BibTeX
@article{sodhani2026beam,
  author  = {Sodhani, Aditya and Kumar, Pavan and Garani, Shayan Srinivasa and Parhi, Keshab K.},
  title   = {Optimizing Encoder Circuits of Entanglement-Assisted Quantum {LDPC} Codes via Beam Search},
  journal = {IEEE Transactions on Circuits and Systems II: Express Briefs},
  year    = {2026},
  doi     = {10.1109/TCSII.2026.3734949}
}

Casts CNOT-count minimization of the standard (SKG) encoder for entanglement-assisted QC-LDPC codes as a GF(2) row-operation decomposition and solves it with Hamming-guided beam search: 7.3–34.0% fewer CNOTs than the SKG construction on all eight codes tested, and fewer than Patel–Markov–Hayes synthesis on every instance. Every circuit is verified by stabilizer-tableau simulation. Joint work with the Indian Institute of Science, Bengaluru.

Encoder Circuit Optimization for Nonbinary Quantum Error Correction Codes in Prime Dimensions: An Algorithmic Framework

Aditya Sodhani, Keshab K. Parhi

IEEE Transactions on Quantum Engineering, vol. 7, pp. 1–15, 2026

DOI IEEE Xplore
BibTeX
@article{sodhani2026nonbinary,
  author  = {Sodhani, Aditya and Parhi, Keshab K.},
  title   = {Encoder Circuit Optimization for Nonbinary Quantum Error Correction Codes in Prime Dimensions: An Algorithmic Framework},
  journal = {IEEE Transactions on Quantum Engineering},
  volume  = {7},
  pages   = {1--15},
  year    = {2026},
  doi     = {10.1109/TQE.2026.3669054}
}

An algorithmic framework over new generating gate sets for synthesizing encoder and decoder circuits of prime-dimension (qudit) stabilizer codes: 13–44% fewer gates for qutrit codes, 9–21% fewer for ququint codes, and 15–42% lower circuit depth than prior constructions.

Talks and posters

Awards and honors

Experience

Education

Contact

sodha005@umn.edu · adityasodhani789@gmail.com

Department of Electrical and Computer Engineering, University of Minnesota, Minneapolis, MN

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